The present invention relates generally to the metallization of layers in semiconductor devices, and in particular to methods of metallizing a copper conductive layer on the surface of a semiconductor wafer using electrochemical deposition.
Metallization is the term used in the semiconductor industry to describe the process for surface wiring the component parts of an integrated circuit. In medium-scale integration only one-level is typically required during the metallization process. In these integrated circuits small contact holes are etched through the surface layers down to the silicon layer during contact masking. After contact masking, a thin metal layer is deposited into the contact holes by many commonly known methods such as vacuum evaporation, sputtering, physical vapor deposition (xe2x80x9cPVDxe2x80x9d) or chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). Aluminum or an aluminum silicon alloy was the primary metal used for the thin metal layer until the introduction of very-large-scale integration (xe2x80x9cVLSIxe2x80x9d) technology and ultra-large-scale integration (xe2x80x9cULSIxe2x80x9d) technology. These VLSI and ULSI semiconductor chips require metal leads with better conductivity and smaller lead sizes capable of carrying large currents.
As known in the art, aluminum suffers from electromigration, which occurs when long skinny leads of aluminum carry high currents over long distances, as is the situation with VLSI and ULSI circuits. Electromigration occurs when the leads in the integrated circuits conduct large amounts of current and become heated, which in turn causes the aluminum that forms the lead to become mobile and diffuse causing a thinning of the lead. Electromigration can cause the chip to fail. Most of the time the chips fail in the field after installation as a result of electromigration. Aluminum-copper alloys have typically been used to try to overcome the problems associated with electromigration, but some electromigration still occurs. In addition, aluminum-copper alloys require complex deposition equipment and processes, cause an increased film resistivity and have different etch rates, thus adding to the complexity of the manufacturing process.
Another problem with using aluminum and aluminum alloys during the metallization process is that aluminum and silicon can dissolve into each other if the leads and silicon are heated to a certain temperature. In the semiconductor industry, this phenomenon is called eutectic formation. A eutectic formation occurs when two materials heated in contact with one another melt at temperatures much lower than their individual melting temperature. The problem with eutectic formations is that in shallow junctions, the alloy region can extend completely through the junction it fills causing it to short out. A method known in the art of preventing eutectic formations is applying a barrier layer between the silicon and the metal conductive layer that interconnects the component parts of the integrated circuit. Titanium-tungsten (TiW), Tantalum (Ta), and titanium nitride (TiN) are commonly used as barrier layers.
Copper metal has begun to replace aluminum and aluminum-silicon alloys in ULSI and VLSI metallization because it has better conductivity, a low RC constant and is more reliable than other metals used to interconnect the circuit component parts of an integrated circuit. The use of electrochemical deposition techniques for copper deposition is especially appealing because of low cost, high throughput, high quality of the deposited copper film and excellent via/trench filling capablities. Although aluminum has a resistance that can be tolerated by most integrated circuits, it is difficult to deposit in a high aspect ratio. Copper, however, is capable of being deposited with high aspect ratios. Also, copper is a better conductor than aluminum, provides good step coverage, is much more resistant to electromigration than aluminum or aluminum alloys, and can be deposited at low temperatures. However, copper will still diffuse into silicon if applied directly to the silicon without first applying a barrier layer.
One issue surrounding electrochemical deposition techniques is the fact that copper does not tend to adhere well to traditional barrier metals. Oxides tend to form on top of the barrier layer before the copper conductive layer can be deposited. In order to solve the problems associated with copper not adhering well to the barrier layer, a copper seed layer is normally deposited on top of the barrier layer. Deposition of the copper seed layer is often applied immediately after the barrier layer is deposited, without even breaking the vacuum used to apply the barrier layer. Because the vacuum remains intact, no oxides can form on the barrier layer before the copper seed layer is applied. Both the barrier layer and the copper seed layer may be deposited by conventional PVD or CVD techniques.
Another problem encountered when electrochemically depositing a metal, such as copper, on the surface of a semiconductor chip is keeping the deposited metal layer homogeneous. Prior methods of electrochemically depositing copper on the surface of a semiconductor device have used a cathodic platter that has a plurality of J-hook fingers, which holds the semiconductor wafer to be plated in place in the electrolytic plating solution. Due to the nature of their design, the J-hook fingers are capable of providing electrical contact to the very edge of the semiconductor wafer, which causes problems with the current density applied to the wafer during electrochemical deposition.
The lack of a uniform current density during electrochemical deposition causes the copper conductive layer deposited on the surface of the semiconductor wafer to be thicker towards the edges of the semiconductor wafer, which is where the J-hook fingers touch the semiconductor wafer, and thinner towards the middle of the semiconductor wafer. This results in higher plating rates around the J-hook fingers, which leads to the buildup of volcano shaped craters with the J-hook finger contact building the deepest point in the middle of the craters. A need exists for a method that allows a copper conductive layer to be directly applied to the semiconductor wafer, while providing a homogeneous deposition by maintaining constant current levels over the entire surface area of the semiconductor wafer during electrochemical deposition.
In view of the above, the present invention provides a method of depositing a copper conductive layer on the surface of a semiconductor wafer including the step of providing a semiconductor wafer having at least one semiconductor device prefabricated on the surface of the semiconductor wafer. The semiconductor device will already be prepared for the metallization process by having a plurality of integrated circuit components already fabricated on the surface of the semiconductor wafer. A cathodic platter is provided that includes a plurality of contact pins that are micro-positioned on a grid type array and held in place by a plurality of connection bars. The cathodic platter serves as the cathode during the electrochemical deposition process. In the disclosed method, the semiconductor wafer is micro-positioned so that the tips of the contact pins are positioned at predefined contact points on the semiconductor wafer containing the semiconductor device to be metallized. After the semiconductor wafer has been micro-positioned on the contact pins a copper conductive layer is electrochemically deposited on the surface of the semiconductor wafer by uniformly applying a current across the surface of the semiconductor wafer.
The electrochemical deposition step can be accomplished using one of two plating techniques. These plating techniques include electroplating and electroless plating, which are especially appealing because of low cost, high throughput, high quality of deposited copper film and excellent via/trench filling capability. Electroplating, in comparison to electroless plating, can provide higher deposition rates. In addition electroplating solutions contain copper ions that are more stable and easier to control than in the case of electroless plating. The present electrochemical deposition method is capable of filling sub-0.5 xcexcm trenches. Electrochemical deposition should be construed to include both electroplating and electroless plating in the present invention.
The present invention overcomes the issues associated with the lack of a uniform current density over the surface area of the semiconductor wafer during electrochemical deposition. In addition, the present invention solves the problems associated with thick deposition of the copper conductive layer on the edge of the semiconductor wafer and thin deposition of the copper conductive layer towards the center of the semiconductor wafer during electrochemical deposition. Using the disclosed method and apparatus results in the deposition of a copper conductive layer that has a regular geometry, is highly conformal and uniformly distributed in the plane of the semiconductor wafer surface. Additionally, the deposited copper conductive layer exhibits the microstructural features of single crystals, which is preferred in the semiconductor industry.
The present invention provides a method of electrochemical deposition, using either electroplating or electroless plating, to deposit a copper conductive layer on the surface of an integrated circuit on a semiconductor wafer. The present invention provides a cathodic platter that is used during the electrochemical deposition process. Using the cathodic platter, the copper conductive layer can be deposited smoothly and evenly, exhibiting a microstructure having the characteristics of a single crystalline structure. Electroplating using the disclosed method and cathodic platter provides high aspect ratios ( greater than 4:1) and defect-free filling of 0.25 xcexcm trenches. In addition, the resistivity of damascene electroplated copper lines has been measured to be about 2 xcexcxcexa9/cm.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.